Virtualbox - Virtualized CPU missing features AVX, AVX2 and FMA - ZhangZhihuiAAA (2025)

(duckdb_book) frank@ZZHUBT:~$ pythonPython 3.13.1 (main, Jan 15 2025, 18:12:47) [GCC 11.4.0] on linuxType "help", "copyright", "credits" or "license" for more information.>>> import polars as pl/home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars/_cpu_check.py:258: RuntimeWarning: Missing required CPU features.The following required CPU features were not detected: avx, avx2, fmaContinuing to use this version of Polars on this processor will likely result in a crash.Install the `polars-lts-cpu` package instead of `polars` to run Polars with better compatibility.Hint: If you are on an Apple ARM machine (e.g. M1) this is likely due to running Python under Rosetta.It is recommended to install a native version of Python that does not run under Rosetta x86-64 emulation.If you believe this warning to be a false positive, you can set the `POLARS_SKIP_CPU_CHECK` environment variable to bypass this check. warnings.warn(Illegal instruction (core dumped)

(duckdb_book) frank@ZZHUBT:~$ lscpuArchitecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 39 bits physical, 48 bits virtual Byte Order: Little EndianCPU(s): 2 On-line CPU(s) list: 0,1Vendor ID: GenuineIntel Model name: 13th Gen Intel(R) Core(TM) i5-1340P CPU family: 6 Model: 186 Thread(s) per core: 1 Core(s) per socket: 2 Socket(s): 1 Stepping: 2 BogoMIPS: 4377.60 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx rdtscp lm constant_tsc rep_good nopl x topology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 cx16 pcid sse4_1 sse4_2 movbe popcnt aes rdrand hypervisor lahf_lm abm 3dnowprefetch ibr s_enhanced fsgsbase bmi1 bmi2 invpcid rdseed adx clflushopt sha_ni arat md_clear flush_l1d arch_capabilitiesVirtualization features: Hypervisor vendor: KVM Virtualization type: fullCaches (sum of all): L1d: 96 KiB (2 instances) L1i: 64 KiB (2 instances) L2: 2.5 MiB (2 instances) L3: 24 MiB (2 instances)NUMA: NUMA node(s): 1 NUMA node0 CPU(s): 0,1Vulnerabilities: Gather data sampling: Not affected Itlb multihit: Not affected L1tf: Not affected Mds: Not affected Meltdown: Not affected Mmio stale data: Not affected Reg file data sampling: Mitigation; Clear Register File Retbleed: Mitigation; Enhanced IBRS Spec rstack overflow: Not affected Spec store bypass: Vulnerable Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Spectre v2: Mitigation; Enhanced / Automatic IBRS; RSB filling; PBRSB-eIBRS SW sequence; BHI SW loop, KVM SW loop Srbds: Not affected Tsx async abort: Not affected

PS C:\Users\ZhangZhihui> wmic cpu get caption, deviceid, name, numberofcores, maxclockspeed, statuswmic : 无法将“wmic”项识别为 cmdlet、函数、脚本文件或可运行程序的名称。请检查名称的拼写，如果包括路径，请确保路径正确，然后再试一次。所在位置 行:1 字符: 1+ wmic cpu get caption, deviceid, name, numberofcores, maxclockspeed, s ...+ ~~~~ + CategoryInfo : ObjectNotFound: (wmic:String) [], CommandNotFoundException + FullyQualifiedErrorId : CommandNotFoundException

PS E:\software\Coreinfo> .\Coreinfo.exeCoreinfo v3.6 - Dump information on system CPU and memory topologyCopyright (C) 2008-2022 Mark RussinovichSysinternals - www.sysinternals.com13th Gen Intel(R) Core(TM) i5-1340PIntel64 Family 6 Model 186 Stepping 2, GenuineIntelMicrocode signature: 00004122HTT * Hyperthreading enabledCET * Supports Control Flow Enforcement TechnologyKernel CET - Kernel-mode CET EnabledUser CET * User-mode CET AllowedHYPERVISOR * Hypervisor is presentVMX - Supports Intel hardware-assisted virtualizationSVM - Supports AMD hardware-assisted virtualizationX64 * Supports 64-bit modeSMX - Supports Intel trusted executionSKINIT - Supports AMD SKINITSGX - Supports Intel SGXNX * Supports no-execute page protectionSMEP * Supports Supervisor Mode Execution PreventionSMAP * Supports Supervisor Mode Access PreventionPAGE1GB * Supports 1 GB large pagesPAE * Supports > 32-bit physical addressesPAT * Supports Page Attribute TablePSE * Supports 4 MB pagesPSE36 * Supports > 32-bit address 4 MB pagesPGE * Supports global bit in page tablesSS * Supports bus snooping for cache operationsVME * Supports Virtual-8086 modeRDWRFSGSBASE * Supports direct GS/FS base accessFPU * Implements i387 floating point instructionsMMX * Supports MMX instruction setMMXEXT - Implements AMD MMX extensions3DNOW - Supports 3DNow! instructions3DNOWEXT - Supports 3DNow! extension instructionsSSE * Supports Streaming SIMD ExtensionsSSE2 * Supports Streaming SIMD Extensions 2SSE3 * Supports Streaming SIMD Extensions 3SSSE3 * Supports Supplemental SIMD Extensions 3SSE4a - Supports Streaming SIMDR Extensions 4aSSE4.1 * Supports Streaming SIMD Extensions 4.1SSE4.2 * Supports Streaming SIMD Extensions 4.2AES * Supports AES extensionsAVX * Supports AVX instruction extensionsAVX2 * Supports AVX2 instruction extensionsAVX-512-F - Supports AVX-512 Foundation instructionsAVX-512-DQ - Supports AVX-512 double and quadword instructionsAVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructionsAVX-512-PF - Supports AVX-512 prefetch instructionsAVX-512-ER - Supports AVX-512 exponential and reciprocal instructionsAVX-512-CD - Supports AVX-512 conflict detection instructionsAVX-512-BW - Supports AVX-512 byte and word instructionsAVX-512-VL - Supports AVX-512 vector length instructionsFMA * Supports FMA extensions using YMM stateMSR * Implements RDMSR/WRMSR instructionsMTRR * Supports Memory Type Range RegistersXSAVE * Supports XSAVE/XRSTOR instructionsOSXSAVE * Supports XSETBV/XGETBV instructionsRDRAND * Supports RDRAND instructionRDSEED * Supports RDSEED instructionCMOV * Supports CMOVcc instructionCLFSH * Supports CLFLUSH instructionCX8 * Supports compare and exchange 8-byte instructionsCX16 * Supports CMPXCHG16B instructionBMI1 * Supports bit manipulation extensions 1BMI2 * Supports bit manipulation extensions 2ADX * Supports ADCX/ADOX instructionsDCA - Supports prefetch from memory-mapped deviceF16C * Supports half-precision instructionFXSR * Supports FXSAVE/FXSTOR instructionsFFXSR - Supports optimized FXSAVE/FSRSTOR instructionMONITOR * Supports MONITOR and MWAIT instructionsMOVBE * Supports MOVBE instructionERMSB * Supports Enhanced REP MOVSB/STOSBPCLMULDQ * Supports PCLMULDQ instructionPOPCNT * Supports POPCNT instructionLZCNT * Supports LZCNT instructionSEP * Supports fast system call instructionsLAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit modeHLE - Supports Hardware Lock Elision instructionsRTM - Supports Restricted Transactional Memory instructionsDE * Supports I/O breakpoints including CR4.DEDTES64 - Can write history of 64-bit branch addressesDS - Implements memory-resident debug bufferDS-CPL - Supports Debug Store feature with CPLPCID * Supports PCIDs and settable CR4.PCIDEINVPCID * Supports INVPCID instructionPDCM * Supports Performance Capabilities MSRRDTSCP * Supports RDTSCP instructionTSC * Supports RDTSC instructionTSC-DEADLINE * Local APIC supports one-shot deadline timerTSC-INVARIANT * TSC runs at constant ratexTPR * Supports disabling task priority messagesEIST * Supports Enhanced Intel SpeedstepACPI * Implements MSR for power managementTM * Implements thermal monitor circuitryTM2 * Implements Thermal Monitor 2 controlAPIC * Implements software-accessible local APICx2APIC * Supports x2APICCNXT-ID - L1 data cache mode adaptive or BIOSMCE * Supports Machine Check, INT18 and CR4.MCEMCA * Implements Machine Check ArchitecturePBE * Supports use of FERR#/PBE# pinPSN - Implements 96-bit processor serial numberPREFETCHW * Supports PREFETCHW instructionMaximum implemented CPUID leaves: 00000020 (Basic), 80000008 (Extended).Maximum implemented address width: 48 bits (virtual), 39 bits (physical).Processor signature: 000B06A2Logical to Physical Processor Map:**-------------- Physical Processor 0 (Hyperthreaded)--**------------ Physical Processor 1 (Hyperthreaded)----**---------- Physical Processor 2 (Hyperthreaded)------**-------- Physical Processor 3 (Hyperthreaded)--------*------- Physical Processor 4---------*------ Physical Processor 5----------*----- Physical Processor 6-----------*---- Physical Processor 7------------*--- Physical Processor 8-------------*-- Physical Processor 9--------------*- Physical Processor 10---------------* Physical Processor 11Logical Processor to Socket Map:**************** Socket 0Logical Processor to NUMA Node Map:**************** NUMA Node 0No NUMA nodes.Logical Processor to Cache Map:**-------------- Data Cache 0, Level 1, 48 KB, Assoc 12, LineSize 64**-------------- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64**-------------- Unified Cache 0, Level 2, 1 MB, Assoc 10, LineSize 64**************** Unified Cache 1, Level 3, 12 MB, Assoc 8, LineSize 64--**------------ Data Cache 1, Level 1, 48 KB, Assoc 12, LineSize 64--**------------ Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64--**------------ Unified Cache 2, Level 2, 1 MB, Assoc 10, LineSize 64----**---------- Data Cache 2, Level 1, 48 KB, Assoc 12, LineSize 64----**---------- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64----**---------- Unified Cache 3, Level 2, 1 MB, Assoc 10, LineSize 64------**-------- Data Cache 3, Level 1, 48 KB, Assoc 12, LineSize 64------**-------- Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64------**-------- Unified Cache 4, Level 2, 1 MB, Assoc 10, LineSize 64--------*------- Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64--------*------- Instruction Cache 4, Level 1, 64 KB, Assoc 8, LineSize 64--------****---- Unified Cache 5, Level 2, 2 MB, Assoc 16, LineSize 64---------*------ Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64---------*------ Instruction Cache 5, Level 1, 64 KB, Assoc 8, LineSize 64----------*----- Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64----------*----- Instruction Cache 6, Level 1, 64 KB, Assoc 8, LineSize 64-----------*---- Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64-----------*---- Instruction Cache 7, Level 1, 64 KB, Assoc 8, LineSize 64------------*--- Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64------------*--- Instruction Cache 8, Level 1, 64 KB, Assoc 8, LineSize 64------------**** Unified Cache 6, Level 2, 2 MB, Assoc 16, LineSize 64-------------*-- Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64-------------*-- Instruction Cache 9, Level 1, 64 KB, Assoc 8, LineSize 64--------------*- Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64--------------*- Instruction Cache 10, Level 1, 64 KB, Assoc 8, LineSize 64---------------* Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64---------------* Instruction Cache 11, Level 1, 64 KB, Assoc 8, LineSize 64Logical Processor to Group Map:**************** Group 0

(duckdb_book) frank@ZZHUBT:~$ pip uninstall polarsFound existing installation: polars 1.19.0Uninstalling polars-1.19.0: Would remove: /home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars-1.19.0.dist-info/* /home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars/*Proceed (Y/n)? Y Successfully uninstalled polars-1.19.0
(duckdb_book) frank@ZZHUBT:~$ pip install polars-lts-cpuCollecting polars-lts-cpu Downloading polars_lts_cpu-1.19.0-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl.metadata (14 kB)Downloading polars_lts_cpu-1.19.0-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (32.4 MB) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ 32.4/32.4 MB 1.6 MB/s eta 0:00:00Installing collected packages: polars-lts-cpuSuccessfully installed polars-lts-cpu-1.19.0

刷新页面返回顶部